//***************************************************************************
//   Copyright(c)2020, Xidian University D405.
//   All rights reserved
//
//   IP Name         :   Null
//   File name       :   cr_fast_to_slow.v
//   Module name     :   cr_fast_to_slow
//   Author          :   Wang Zekun
//   Date            :   2022/06/30
//   Version         :   v1.0
//   Verison History :   v1.0/
//   Edited by       :   Wang Zekun
//   Modification history : v1.0 Initial revision
//
// ----------------------------------------------------------------------------
// Version 1.0       Date(2022/06/30)
// Abstract : sync 312.5MHz signals to 62.5MHz 
//
//-----------------------------------------------------------------------------
// Programmer's model
//
//-----------------------------------------------------------------------------
//interface list :
//                

module cr_fast_to_slow (
    input  wire                           clk_f_i,
    input  wire                           resetn_f_i,
    input  wire                           signal_f_i,
    input  wire                           clk_s_i,
    input  wire                           resetn_s_i,
    output wire                           signal_s_o
  );

  reg [4:0]         reg_shift;
  reg               signal_s;

  always @(posedge clk_f_i or negedge resetn_f_i) begin
    if(~resetn_f_i) begin
      reg_shift <= 5'b000;
    end
    else begin
      reg_shift <= {reg_shift[3:0],signal_f_i};
    end
  end

  always @(posedge clk_s_i or negedge resetn_s_i) begin
    if(~resetn_s_i) begin
      signal_s <= 1'b0;
    end
    else begin
      signal_s <= |reg_shift;
    end
  end

  assign signal_s_o= signal_s;
endmodule
